Methods of Forming Dual-Damascene Metal Wiring Patterns for Integrated Circuit Devices and Wiring Patterns Formed Thereby

ABSTRACT

Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer. The first portion of the etch-stop layer is then selectively etched for a sufficient duration to expose a portion of the first metal wiring pattern. A second metal wiring pattern is formed in the opening in order to complete a dual-damascene structure.

REFERENCE TO PRIORITY APPLICATION

This application claims priority to Korean Patent Application No.2005-72006, filed Aug. 6, 2005, the disclosure of which is herebyincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to methods of forming metal wiringpatterns and, more particularly, to methods of forming metal wiringpatterns using dual-damascene techniques and metal wiring patternsformed thereby.

BACKGROUND OF THE INVENTION

Metal wiring patterns used in integrated circuit devices are frequentlyformed of copper (Cu) because copper has a relatively low resistivity,particularly compared to metal wiring patterns formed of other materialssuch as aluminum (Al). These metal wiring patterns are frequentlyseparated from each other by intermetal dielectric layers. In order toreduce the parasitic capacitance between adjacent metal wiring patternsand reduce their RC delay, dielectric layers having relatively lowdielectric constant values (i.e., low-K dielectrics) have been used asintermetal dielectric layers.

Damascene processing techniques that utilize low-K dielectrics have beenused to define copper wiring patterns on integrated circuit substrates.These techniques frequently include forming a low-K dielectric layer ona first copper wiring pattern and then forming via holes and trenches inthe low-K dielectric layer, which expose upper surfaces of the firstcopper wiring pattern. These via holes and trenches are then filled witha copper wiring layer, which may be formed using an electroplatingtechnique. Planarization techniques such as chemical-mechanicalpolishing (CMP), may then be used to planarize the copper wiring layerinto a plurality of second copper wiring patterns and thereby complete adual-damascene wiring fabrication process.

An example of a conventional dual-damascene processing technique isillustrated by FIGS. 1A-1D. In FIG. 1A, a first low-K dielectric layer10 is formed on a substrate (e.g., semiconductor substrate). This firstlow-K dielectric layer 10 may be patterned to define a trench therein,which is subsequently filled with a lower metal line 12 (e.g., copperline). An etch stop layer 14 and an electrically insulating layer 16(e.g, silicon dioxide) are formed on the first low-K dielectric layer10, as illustrated. Thereafter, as illustrated by FIG. 1B, a secondlow-K dielectric layer 17 is formed on the electrically insulating layer16. Conventional patterning and etching steps are then performed todefine a via hole/trench 18 that extends through the second low-Kdielectric layer 17, the electrically insulating layer 16 and the etchstop layer 14, and exposes the lower metal line 12. As illustrated,these patterning and etching steps may result in the formation of a viahole 18 that defines a recess in the lower metal line 12. As will beunderstood by those skilled in the art, the formation of a recess in thelower metal line 12 and the exposure of this recess to an oxygencontaining ambient may result in the formation of an oxide residue (notshown) on the lower metal line 12. This oxide residue may be removed byexposing the lower metal line 12 to a wet cleaning solution containing,for example, diluted HF (DHF). However, this exposure to the wetcleaning solution may also result in the formation of undercut regions20 within the electrically insulating layer 16, which may react with thecleaning solution.

Referring now to FIG. 1C, a step is performed to deposit a first barriermetal layer in the via hole 18 using a physical vapor deposition (PVD)technique, for example. This first barrier metal layer may be a tantalumnitride layer having a thickness in a range from about 50 Å to about 100Å. This first barrier metal layer operates as a copper diffusion barrierduring subsequent processing steps. Unfortunately, the presence of theundercut regions 20 may preclude the formation of a uniform firstbarrier metal layer on the sidewall of the via hole 18. A directionaletching step may then be performed to remove a portion of the firstbarrier metal layer from an upper surface of the lower metal line 12 andthereby pattern the first barrier metal layer into sidewall barriersegments 22. This removal of the first barrier metal layer from thelower metal line 12 may operate to decrease the contact resistancebetween lower metal line 12 and a subsequently formed copper plug.

As will be understood by those skilled in the art, the directionaletching of the first barrier metal layer to achieve exposure of theupper surface of the lower metal line 12 may result in the formation ofresputtered copper spacers 24 on lower sidewalls of the via hole 18.Because of the presence of the undercut regions 20, which may not besufficiently protected by the sidewall barrier segments 22, copper atomsfrom the copper spacers 24 may become incorporated into the second low-Kdielectric layer 17. Such penetration of copper into the second low-Kdielectric layer 17 may increase leakage currents between adjacent metallines formed in the second low-K dielectric layer 17. This increase inleakage current may degrade device reliability by increasing timedependent dielectric breakdown (TDDB) within the second low-K dielectriclayer 17.

Referring now to FIG. 1D, a second barrier metal layer 26 is thenconformally deposited into the via hole 18 using, for example, physicalvapor deposition (PVD). This second barrier metal layer 26 may be anadhesion enhancing tantalum layer (Ta) having a thickness in a rangefrom about 40 Å to about 200 Å. A blanket copper seed layer (not shown)may then be deposited on the second barrier metal layer 26 and followedby copper electroplating to fill the via hole 18. Planarizationtechniques may then be performed to define an upper metal line 28 withinthe via hole 18.

SUMMARY OF THE INVENTION

Embodiments of the present invention include methods of forming anintegrated circuit by forming a first metal wiring pattern (e.g., copperwiring pattern) on an integrated circuit substrate and forming anetch-stop layer on the first metal wiring pattern. These steps arefollowed by forming an electrically insulating layer on the etch-stoplayer and forming an inter-metal dielectric layer on the electricallyinsulating layer. The inter-metal dielectric layer and the electricallyinsulating layer are selectively etched in sequence to define an openingtherein that exposes a first portion of the etch-stop layer. Thisopening may include a trench and a via hole extending downward from abottom of the trench. A first barrier metal layer is formed on asidewall of the opening and directly on the first portion of theetch-stop layer. A portion of the first barrier metal layer isselectively removed from the first portion of the etch-stop layer. Thisselective removal may be performed using an anisotropic etching step.The first portion of the etch-stop layer is then selectively etched fora sufficient duration to expose a portion of the first metal wiringpattern. During this etching step, the first barrier metal layer is usedas an etching mask. A second metal wiring pattern (e.g., upper copperwiring pattern) is then formed in the opening in order to complete adual-damascene structure.

According to further aspects of these embodiments, the step of forming asecond metal wiring pattern may be preceded by a step of forming asecond barrier metal layer on the sidewall of the opening and on theexposed portion of the first metal wiring pattern. In the event thesecond barrier metal layer is formed, then a step may be performed toselectively etch a portion of the second barrier metal layer for asufficient duration to expose the portion of the first metal wiringpattern.

Still further embodiments of the present invention include methods offorming an integrated circuit by forming a first copper wiring patternon an integrated circuit substrate and forming an etch-stop layercomprising SiCN on the first copper wiring pattern. A silicon dioxidelayer having a thickness in a range from about 100 Å to about 500 Å isformed on the etch-stop layer and a inter-metal dielectric layercomprising SiCOH is formed on the silicon dioxide layer. The inter-metaldielectric layer and the silicon dioxide layer are selectively etched insequence to define an opening therein that exposes a first portion ofthe etch-stop layer. A first barrier metal layer comprising tantalum isformed on a sidewall of the opening and directly on the first portion ofthe etch-stop layer. A portion of the first barrier metal layer isselectively removed from the first portion of the etch-stop layer. Thefirst portion of the etch-stop layer is etched for a sufficient durationto expose a portion of an upper surface of the first copper wiringpattern. During this etching step, the first barrier metal layer is usedas an etching mask. A second barrier metal layer containing tantalum isthen formed, which extends on the first barrier metal layer, a sidewallof the etch-stop layer and the exposed portion of the first copperwiring pattern. The second barrier metal layer is selectively etched toexpose the first copper wiring pattern. A third barrier metal layercontaining tantalum is formed on the second barrier metal layer anddirectly on the first copper wiring pattern. Thereafter, the opening isfilled with a second copper wiring pattern to complete thedual-damascene copper interconnect structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1D are cross-sectional views of intermediate structures thatillustrate conventional methods of forming dual-damascene copperinterconnect structures for integrated circuits.

FIGS. 2A-2H are cross-sectional views of intermediate structures thatillustrate methods of forming dual-damascene copper interconnectstructures for integrated circuits, according to embodiments of thepresent invention.

FIGS. 2A-2E and 3 are cross-sectional views of intermediate structuresthat illustrate methods of forming dual-damascene copper interconnectstructures for integrated circuits, according to embodiments of thepresent invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention now will be described more fully herein withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as being limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. Likereference numerals refer to like elements throughout.

Methods of forming dual-damascene copper interconnect structuresaccording to embodiments of the present invention include forming afirst dielectric layer 205 on a primary surface of a semiconductorsubstrate 203 having a plurality of active semiconductor devices (notshown) therein. This first dielectric layer 205 may be a low-Kdielectric layer, such as SiCOH, having a thickness in a range fromabout 2,000 Å to about 20,000 Å. Thereafter, the first dielectric layer205 is patterned to define a recess/trench therein. This recess/trenchis lined with a lower barrier metal layer 207 (e.g., tantalum (Ta)) andfilled with a lower metal line 210 (e.g., Copper (Cu)) usingconventional techniques. A chemical mechanical polishing (CMP) step maybe performed to planarize the lower metal line 210 with an upper surfaceof the first dielectric layer 205. An etch-stop layer 212 is thendeposited onto the first dielectric layer 205. This etch-stop layer 212may have a thickness in a range from about 200 Å to about 1000 Å and maybe formed of a material such as SiCN. The etch-stop layer 212 may bedeposited using a chemical-vapor deposition (CVD) technique, forexample.

Referring still to FIG. 2A, a second interlayer-dielectric layer 220 isformed on the etch-stop layer 212. This second interlayer-dielectriclayer 220 includes a first insulating layer 214, which may be formed ofsilicon dioxide, and a second insulating layer 216, which may be a low-Kdielectric layer (e.g., SiCOH layer). The first insulating layer 214 mayhave a thickness in a range from about 100 Å to about 5000 Å and thesecond insulating layer 216 may have a thickness in a range from about2,000 Å to about 10,000 Å. A hard mask layer 225 is deposited onto thesecond interlayer-dielectric layer 220. This hard mask layer 225 may bea silicon dioxide layer having a thickness in a range from about 200 Åto about 1,500 Å.

Referring now to FIG. 2B, a plurality of selective etching andpatterning steps (e.g., photolithographically-defined etching steps) arethen performed on the structure illustrated by FIG. 2A. In particular,the hard mask layer 225 and the second interlayer-dielectric layer 220are selectively etched to define a via hole 230 and a trench 235therein, as illustrated. The via hole 230 may be a generally cylindricalvia hole 230 of limited lateral dimension, but the trench may besubstantially larger and extend laterally as a trench pattern in a thirddimension (not shown). The etch-stop layer 212 is configured to blockexposure of the lower metal line 210 during the selective etching stepsto define the via hole 230.

Referring now to FIG. 2C, a first barrier metal layer 240 is thenconformally deposited onto the structure illustrated by FIG. 2B. Thisfirst barrier metal layer 240, which lines sidewalls of the trench 235and via hole 230, may be a tantalum layer, a tantalum nitride layer or acomposite layer containing tantalum and tantalum nitride. The firstbarrier metal layer 240 may have a thickness in a range from about 30 Åto about 100 Å. Thereafter, as illustrated by FIG. 2D, an anisotropicetching step is performed to selectively etch horizontal portions of thefirst barrier metal layer 240 and define first barrier metal layerspacers 240 a on sidewalls of the via hole 230 and trench 235. Thesefirst barrier metal layer spacers 240 a may then be used as an etchingmask during an etching step that selectively removes an exposed portionof the etch-stop layer 212. This removal of an exposed portion of theetch-stop layer 212 results in an exposure of a portion of an uppersurface 218 of the lower metal line 210.

Any formation of a native oxide on the exposed portion of the uppersurface 218 of the lower metal line 210 may be removed using a wetcleaning process. This cleaning process may involve exposing the surface218 to a cleaning solution containing diluted hydrofluoric acid (DHF).During this cleaning process, the first barrier metal layer spacers 240a operate to inhibit lateral chemical etching of the first insulatinglayer 214 by DHF. Alternatively, a sputter etching technique may be usedto remove any native oxide from the upper surface 218.

Referring now to FIG. 2E, a second barrier metal layer 245 is thenconformally deposited into the via hole 230 and trench 235 in order tocover and protect exposed portions of the second insulating layer 216and cover and protect exposed sidewalls of the etch-stop layer 212. Thissecond barrier metal layer 245 may be a tantalum layer, a tantalumnitride layer or a composite layer containing tantalum and tantalumnitride. This second barrier metal layer 245 may have a thickness in arange from about 30 Å to about 100 Å. A step is then performed to removea portion of the second barrier metal layer 245 that extends on theupper surface of the lower metal line 210. This removal step, which maybe performed as a sputter etching step, may result in a partial removaland respuftering of the lower metal line 210 onto sidewalls of thesecond barrier metal layer 245, to thereby define a recessed surface 218a of the lower metal line 210. These resputtered portions of the lowermetal line 210, which may have a thickness in a range from about 10 Å toabout 300 Å, are identified by the reference numeral 210 a.

Referring now to FIG. 2F, a third barrier metal layer 250 is thenconformally deposited into the via hole 230 and trench 235 to therebycover the second barrier metal layer 245. This third barrier metal layer250 may have a thickness in a range from about 100 Å to about 500 Å. Thethird barrier metal layer 250 may be formed as a tantalum or tantalumnitride layer, however, tantalum is typically preferred because it has alower resistivity relative to tantalum nitride.

Finally, as illustrated by FIGS. 2G-2H ₁ a metallization layer 255 isthen deposited onto the structure of FIG. 2F to thereby completely fillthe via hole 230 and trench 235. This metallization layer 255 may bedeposited by electroplating copper from a copper seed layer (not shown)formed within the via hole 230. In alternative embodiments, themetallization layer 255 may be formed using chemical vapor deposition(CVD) and/or physical vapor deposition (PVD) techniques. Themetallization layer 255 is then planarized to define an upper metal line255 b in the trench 235, which extends in a third dimension (not shown),and define a metal plug 255 a within the via hole 230. Thisplanarization step may be performed by chemically-mechanically polishingthe metallization layer 255 for a sufficient duration to expose thesecond insulating layer 216.

Still further embodiments of the present invention are illustrated byFIGS. 2A-2E and 3. In particular, FIG. 3 illustrates the steps ofdepositing a metallization layer 255 onto the structure of FIG. 2E tothereby completely fill the via hole 230 and trench 235. Thismetallization layer 255 may be deposited by electroplating copper from acopper seed layer (not shown) formed within the via hole 230. Inalternative embodiments, the metallization layer 255 may be formed usingchemical vapor deposition (CVD) and/or physical vapor deposition (PVD)techniques. The metallization layer 255 is then planarized to define anupper metal line 255 b in the trench 235, which extends in a thirddimension (not shown), and define a metal plug 255 a within the via hole230. This planarization step may be performed by chemically-mechanicallypolishing the metallization layer 255 for a sufficient duration toexpose the second insulating layer 216.

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being set forthin the following claims.

1. A method of forming an integrated circuit, comprising the steps of:forming a first metal wiring pattern on an integrated circuit substrate;forming an etch-stop layer on the first metal wiring pattern; forming anelectrically insulating layer on the etch-stop layer; forming aninter-metal dielectric layer on the electrically insulating layer;selectively etching the inter-metal dielectric layer and theelectrically insulating layer in sequence to define an opening thereinthat exposes a first portion of the etch-stop layer; forming a firstbarrier metal layer on a sidewall of the opening and directly on thefirst portion of the etch-stop layer; selectively removing a portion ofthe first barrier metal layer from the first portion of the etch-stoplayer; then selectively etching the first portion of the etch-stop layerfor a sufficient duration to expose a portion of the first metal wiringpattern, using the first barrier metal layer as an etching mask; andthen forming a second metal wiring pattern in the opening.
 2. The methodof claim 1, wherein said step of forming a second metal wiring patternis preceded by a step of forming a second barrier metal layer on thesidewall of the opening and on the exposed portion of the first metalwiring pattern.
 3. The method of claim 2, wherein said step of forming asecond barrier metal layer is followed by a step of selectively etchinga portion of the second barrier metal layer for a sufficient duration toexpose the portion of the first metal wiring pattern.
 4. The method ofclaim 2, wherein said step of forming a second barrier metal layer isfollowed by a step of selectively etching a portion of the secondbarrier metal layer and the first metal wiring pattern in sequence todefine a recess within an upper surface of the first metal wiringpattern.
 5. The method of claim 4, wherein said step of forming a secondmetal wiring pattern is preceded by a step of forming a third barriermetal layer on the recess within the first metal wiring pattern.
 6. Themethod of claim 1, wherein said step of forming an etch-stop layercomprises forming a SiCN layer having a thickness in a range from about200 Å to about 1,000 Å on the first metal wiring pattern.
 7. The methodof claim 1, wherein said step of forming an inter-metal dielectric layercomprises forming a SiCOH layer having a thickness in a range from about2,000 Å to about 10,000 Å on the electrically insulating layer.
 8. Themethod of claim 1, wherein said step of forming a first barrier metallayer comprises forming a metal layer comprising tantalum on thesidewall of the opening and directly on the first portion of theetch-stop layer.
 9. The method of claim 1, wherein said step of forminga second metal wiring pattern is preceded by a step of exposing thefirst metal wiring pattern to a diluted HF cleaning solution.
 10. Amethod of forming an integrated circuit device, comprising the steps of:forming a first electrically conductive wiring pattern on an integratedcircuit substrate; forming first and second electrically insulatinglayers of different material type on the first electrically conductivewiring pattern; selectively etching the second electrically insulatinglayer for a sufficient duration to define an opening therein thatexposes a portion of the first electrically insulating layer; forming afirst barrier metal layer on a sidewall of the opening and directly onthe portion of the first electrically insulating layer; selectivelyremoving a portion of the first barrier metal layer from the portion ofthe first electrically insulating layer; then selectively etching theportion of the first electrically insulating layer for a sufficientduration to expose a portion of the first electrically conductive wiringpattern, using the first barrier metal layer as an etching mask; andthen forming a second electrically conductive wiring pattern in theopening.
 11. The method of claim 10, wherein the first electricallyinsulating layer is a SiCN layer having a thickness in a range fromabout 200 Å to about 1,000 Å.
 12. The method of claim 11, wherein thesecond electrically insulating layer is a SiCOH layer having a thicknessin a range from about 2,000 Å to about 10,0000 Å.
 13. The method ofclaim 12, wherein the first barrier metal layer is a metal layercomprising tantalum and having a thickness in a range from about 30 Å toabout 100 Å.
 14. The method of claim 10, wherein said step of forming asecond electrically conductive wiring pattern is preceded by the step offorming a second barrier metal layer comprising tantalum on the exposedportion of the first electrically conductive wiring pattern.
 15. Amethod of forming an integrated circuit, comprising the steps of:forming a first copper wiring pattern on an integrated circuitsubstrate; forming an etch-stop layer comprising SiCN on the firstcopper wiring pattern; forming a silicon dioxide layer having athickness in a range from about 100 Å to about 500 Å on the etch-stoplayer; forming an inter-metal dielectric layer comprising SiCOH on thesilicon dioxide layer; selectively etching the inter-metal dielectriclayer and the silicon dioxide layer in sequence to define an openingtherein that exposes a first portion of the etch-stop layer; forming afirst barrier metal layer comprising tantalum on a sidewall of theopening and directly on the first portion of the etch-stop layer;selectively removing a portion of the first barrier metal layer from thefirst portion of the etch-stop layer; then selectively etching the firstportion of the etch-stop layer for a sufficient duration to expose aportion of the first copper wiring pattern, using the first barriermetal layer as an etching mask; forming a second barrier metal layercomprising tantalum that extends on the first barrier metal layer, asidewall of the etch-stop layer and the exposed portion of the firstcopper wiring pattern; selectively etching the second barrier metallayer to expose the first copper wiring pattern; then forming a thirdbarrier metal layer comprising tantalum on the second barrier metallayer and on the first copper wiring pattern; and then filling theopening with a second copper wiring pattern.
 16. The method of claim 15,wherein said step of selectively etching the inter-metal dielectriclayer and the silicon dioxide layer in sequence is preceded by a step offorming a silicon dioxide hard mask layer on the inter-metal dielectriclayer.
 17. The method of claim 15, wherein said step of forming anetch-stop layer comprises forming a SiCN layer having a thickness in arange from about 100 Å to about 500 Å, on the first copper wiringpattern.
 18. A dual-damascene wiring pattern of an integrated circuit,comprising: a first metal wiring pattern on an integrated circuitsubstrate; an inter-metal dielectric layer extending on the integratedcircuit substrate, said inter-metal dielectric layer having a via holetherein that extends opposite an upper surface of said first metalwiring pattern; a first barrier metal layer lining a sidewall of the viahole; an etch-stop layer extending between the upper surface of saidfirst metal wiring pattern and said inter-metal dielectric layer, saidetch-stop layer having an opening therein that is self-aligned to saidfirst barrier metal layer; and a second metal wiring pattern thatextends into the via hole and opening, and is electrically connected tosaid first metal wiring pattern.
 19. The wiring pattern of claim 18,wherein the inter-metal dielectric layer comprises a first insulatinglayer and a second insulating layer formed on the first insulatinglayer.
 20. The wiring pattern of claim 19, wherein the first insulatinglayer is an oxide layer and the second insulating layer has a dielectricconstant less than a dielectric constant of the oxide layer.
 21. Thewiring pattern of claim 20, wherein the second insulating layer is anSiCOH layer and the etch-stop layer is an SiCN layer.
 22. The wiringpattern of claim 18, wherein the first metal wiring pattern is a coppermetal wiring pattern.
 23. The wiring pattern of claim 18, furthercomprising a second barrier metal layer that lines a sidewall of theopening in the etch-stop layer.
 24. The wiring pattern of claim 23,further comprising a third barrier metal layer that extends between asidewall of the etch-stop layer and the second metal wiring pattern. 25.The wiring pattern of claim 24, wherein the first barrier metal layercomprises tantalum nitride and the third barrier metal layer comprisestantalum.
 26. A wiring pattern of an integrated circuit, comprising: afirst electrically conductive pattern on an integrated circuitsubstrate; a second electrically insulating layer on the integratedcircuit substrate, said first electrically conductive pattern having avia hole therein that extends opposite an upper surface of said firstelectrically conductive pattern; a first barrier metal layer lining asidewall of the via hole; a first electrically insulating layerextending between the upper surface of the first electrically conductivepattern and said second electrically insulating layer, said firstelectrically insulating layer having an opening therein that isself-aligned to said first barrier metal layer; and a secondelectrically conductive pattern that extends into the via hole andopening, and is electrically connected to said first electricallyconductive pattern.